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<a href="#define-members">Macros</a>  </div>
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<div class="title">Interrupt Masks<div class="ingroups"><a class="el" href="group__group__sar.html">SAR          (SAR ADC Subsystem)</a> &raquo; <a class="el" href="group__group__sar__macros.html">Macros</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
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Macros</h2></td></tr>
<tr class="memitem:ga9538a57901b8fab401b60e71834d3971"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga9538a57901b8fab401b60e71834d3971">CY_SAR_INTR_EOS</a>&#160;&#160;&#160;(SAR_INTR_MASK_EOS_MASK_Msk)</td></tr>
<tr class="memdesc:ga9538a57901b8fab401b60e71834d3971"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt masks.  <a href="#ga9538a57901b8fab401b60e71834d3971">More...</a><br /></td></tr>
<tr class="separator:ga9538a57901b8fab401b60e71834d3971"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga880d26ca6d3f4ba0ef484a1009b02ce4"><td class="memItemLeft" align="right" valign="top"><a id="ga880d26ca6d3f4ba0ef484a1009b02ce4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga880d26ca6d3f4ba0ef484a1009b02ce4">CY_SAR_INTR_OVERFLOW</a>&#160;&#160;&#160;(SAR_INTR_MASK_OVERFLOW_MASK_Msk)</td></tr>
<tr class="memdesc:ga880d26ca6d3f4ba0ef484a1009b02ce4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable overflow interrupt. <br /></td></tr>
<tr class="separator:ga880d26ca6d3f4ba0ef484a1009b02ce4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab899a78469af6a37779035df455ed8be"><td class="memItemLeft" align="right" valign="top"><a id="gab899a78469af6a37779035df455ed8be"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#gab899a78469af6a37779035df455ed8be">CY_SAR_INTR_FW_COLLISION</a>&#160;&#160;&#160;(SAR_INTR_MASK_FW_COLLISION_MASK_Msk)</td></tr>
<tr class="memdesc:gab899a78469af6a37779035df455ed8be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable firmware collision interrupt. <br /></td></tr>
<tr class="separator:gab899a78469af6a37779035df455ed8be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8c5ea0bef42743baf6520a1a7ae944f"><td class="memItemLeft" align="right" valign="top"><a id="gab8c5ea0bef42743baf6520a1a7ae944f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#gab8c5ea0bef42743baf6520a1a7ae944f">CY_SAR_INTR_INJ_EOC</a>&#160;&#160;&#160;(SAR_INTR_INJ_EOC_INTR_Msk)</td></tr>
<tr class="memdesc:gab8c5ea0bef42743baf6520a1a7ae944f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable injection channel end of conversion (EOC) interrupt. <br /></td></tr>
<tr class="separator:gab8c5ea0bef42743baf6520a1a7ae944f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d32445b6c10affe742671b9f34f1772"><td class="memItemLeft" align="right" valign="top"><a id="ga2d32445b6c10affe742671b9f34f1772"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga2d32445b6c10affe742671b9f34f1772">CY_SAR_INTR_INJ_SATURATE</a>&#160;&#160;&#160;(SAR_INTR_INJ_SATURATE_INTR_Msk)</td></tr>
<tr class="memdesc:ga2d32445b6c10affe742671b9f34f1772"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable injection channel saturation interrupt. <br /></td></tr>
<tr class="separator:ga2d32445b6c10affe742671b9f34f1772"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga871f25e3359700ab3a7b9ffadc0adc90"><td class="memItemLeft" align="right" valign="top"><a id="ga871f25e3359700ab3a7b9ffadc0adc90"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga871f25e3359700ab3a7b9ffadc0adc90">CY_SAR_INTR_INJ_RANGE</a>&#160;&#160;&#160;(SAR_INTR_INJ_RANGE_INTR_Msk)</td></tr>
<tr class="memdesc:ga871f25e3359700ab3a7b9ffadc0adc90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable injection channel range detection interrupt. <br /></td></tr>
<tr class="separator:ga871f25e3359700ab3a7b9ffadc0adc90"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6374f1aaff33347a1adf7d31c08f58ef"><td class="memItemLeft" align="right" valign="top"><a id="ga6374f1aaff33347a1adf7d31c08f58ef"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga6374f1aaff33347a1adf7d31c08f58ef">CY_SAR_INTR_INJ_COLLISION</a>&#160;&#160;&#160;(SAR_INTR_INJ_COLLISION_INTR_Msk)</td></tr>
<tr class="memdesc:ga6374f1aaff33347a1adf7d31c08f58ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable injection channel firmware collision interrupt. <br /></td></tr>
<tr class="separator:ga6374f1aaff33347a1adf7d31c08f58ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4631d21a955c1b3153c68f14d124f3d9"><td class="memItemLeft" align="right" valign="top"><a id="ga4631d21a955c1b3153c68f14d124f3d9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga4631d21a955c1b3153c68f14d124f3d9">CY_SAR_INTR_FIFO_LEVEL</a>&#160;&#160;&#160;(PASS_FIFO_V2_INTR_FIFO_LEVEL_Msk)</td></tr>
<tr class="memdesc:ga4631d21a955c1b3153c68f14d124f3d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable FIFO level interrupt. <br /></td></tr>
<tr class="separator:ga4631d21a955c1b3153c68f14d124f3d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00e87ae8adaeda977189f9e56b47d1fa"><td class="memItemLeft" align="right" valign="top"><a id="ga00e87ae8adaeda977189f9e56b47d1fa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga00e87ae8adaeda977189f9e56b47d1fa">CY_SAR_INTR_FIFO_OVERFLOW</a>&#160;&#160;&#160;(PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Msk)</td></tr>
<tr class="memdesc:ga00e87ae8adaeda977189f9e56b47d1fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable FIFO overflow interrupt. <br /></td></tr>
<tr class="separator:ga00e87ae8adaeda977189f9e56b47d1fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7082c07883675f86f026260c7a9c8cb3"><td class="memItemLeft" align="right" valign="top"><a id="ga7082c07883675f86f026260c7a9c8cb3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga7082c07883675f86f026260c7a9c8cb3">CY_SAR_INTR_FIFO_UNDERFLOW</a>&#160;&#160;&#160;(PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Msk)</td></tr>
<tr class="memdesc:ga7082c07883675f86f026260c7a9c8cb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable FIFO underflow interrupt. <br /></td></tr>
<tr class="separator:ga7082c07883675f86f026260c7a9c8cb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga471233cf915dda88b9d6b1a272d26ee2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga471233cf915dda88b9d6b1a272d26ee2">CY_SAR_INTR</a></td></tr>
<tr class="memdesc:ga471233cf915dda88b9d6b1a272d26ee2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Combined interrupt mask.  <a href="#ga471233cf915dda88b9d6b1a272d26ee2">More...</a><br /></td></tr>
<tr class="separator:ga471233cf915dda88b9d6b1a272d26ee2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0cee3edaac22c1f36d5b5bbef695a6f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__macros__interrupt.html#ga0cee3edaac22c1f36d5b5bbef695a6f6">CY_SAR_INTR_FIFO</a></td></tr>
<tr class="memdesc:ga0cee3edaac22c1f36d5b5bbef695a6f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Combined interrupt mask for FIFO.  <a href="#ga0cee3edaac22c1f36d5b5bbef695a6f6">More...</a><br /></td></tr>
<tr class="separator:ga0cee3edaac22c1f36d5b5bbef695a6f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga9538a57901b8fab401b60e71834d3971"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9538a57901b8fab401b60e71834d3971">&#9670;&nbsp;</a></span>CY_SAR_INTR_EOS</h2>

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          <td class="memname">#define CY_SAR_INTR_EOS&#160;&#160;&#160;(SAR_INTR_MASK_EOS_MASK_Msk)</td>
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<p>Interrupt masks. </p>
<p>Enable end of scan (EOS) interrupt </p>

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<a id="ga471233cf915dda88b9d6b1a272d26ee2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga471233cf915dda88b9d6b1a272d26ee2">&#9670;&nbsp;</a></span>CY_SAR_INTR</h2>

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          <td class="memname">#define CY_SAR_INTR</td>
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<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__group__sar__macros__interrupt.html#ga9538a57901b8fab401b60e71834d3971">CY_SAR_INTR_EOS</a> | \</div><div class="line">                                         CY_SAR_INTR_OVERFLOW | \</div><div class="line">                                         CY_SAR_INTR_FW_COLLISION | \</div><div class="line">                                         CY_SAR_INTR_INJ_EOC | \</div><div class="line">                                         CY_SAR_INTR_INJ_SATURATE | \</div><div class="line">                                         CY_SAR_INTR_INJ_RANGE | \</div><div class="line">                                         CY_SAR_INTR_INJ_COLLISION)</div><div class="ttc" id="group__group__sar__macros__interrupt_html_ga9538a57901b8fab401b60e71834d3971"><div class="ttname"><a href="group__group__sar__macros__interrupt.html#ga9538a57901b8fab401b60e71834d3971">CY_SAR_INTR_EOS</a></div><div class="ttdeci">#define CY_SAR_INTR_EOS</div><div class="ttdoc">Interrupt masks. </div><div class="ttdef"><b>Definition:</b> cy_sar.h:729</div></div>
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<p>Combined interrupt mask. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0cee3edaac22c1f36d5b5bbef695a6f6">&#9670;&nbsp;</a></span>CY_SAR_INTR_FIFO</h2>

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          <td class="memname">#define CY_SAR_INTR_FIFO</td>
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<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__group__sar__macros__interrupt.html#ga4631d21a955c1b3153c68f14d124f3d9">CY_SAR_INTR_FIFO_LEVEL</a> | \</div><div class="line">                                         CY_SAR_INTR_FIFO_OVERFLOW | \</div><div class="line">                                         CY_SAR_INTR_FIFO_UNDERFLOW)</div><div class="ttc" id="group__group__sar__macros__interrupt_html_ga4631d21a955c1b3153c68f14d124f3d9"><div class="ttname"><a href="group__group__sar__macros__interrupt.html#ga4631d21a955c1b3153c68f14d124f3d9">CY_SAR_INTR_FIFO_LEVEL</a></div><div class="ttdeci">#define CY_SAR_INTR_FIFO_LEVEL</div><div class="ttdoc">Enable FIFO level interrupt. </div><div class="ttdef"><b>Definition:</b> cy_sar.h:736</div></div>
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<p>Combined interrupt mask for FIFO. </p>

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